A semiconductor nonvolatile memory is frequently used for mobile equipment such as a mobile phone, and in recent years, a market thereof has been increasingly spread. Currently, the semiconductor nonvolatile memory which is most utilized is a FLASH memory. However, since a rewriting speed thereof is essentially slow, it is mainly used as a programmable ROM, an information storage device for a still camera, in which the rewriting is not frequently performed, or the like. Also, since the FLASH memory requires large power consumption at the rewriting time, it includes a large issue from the viewpoint of reduction of battery exhaustion which is important for mobile terminal equipment.
On the other hand, since a high-speed RAM is required as a working memory, both memories of the FLASH memory and a DRAM are mixedly mounted in the mobile terminal equipment. If a device provided with characteristics of these two memories can be realized, an impact of the device is extremely large in that it becomes possible not only to integrate the FLASH memory and the DRAM on one chip but also to replace all semiconductor memories with the device.
As one of candidates for realizing the device which has low power consumption and high rewriting speed and is suitable also for the working memory of the mobile terminal equipment, there is a nonvolatile memory using a phase change film.
As already known, materials capable of switching reversibly from one phase to the other phase are used for the phase change memory. A reading is possible by a difference between electric characteristics of these phase states. For example, these materials can change between a disordered phase of an amorphous state and an ordered phase of a crystal state. The amorphous state has an electric resistance higher than that of the crystal state, so that information can be stored by using the difference between the electric resistances.
The material suitable for the phase change memory cell is an alloy containing at least one element of sulfur, selenium, and tellurium, such an alloy being called “chalcogenide”. Currently, a most coming chalcogenide is an alloy made of germanium, antimony, and tellurium (Ge2Sb2Te5), and the alloy has been already widely used for information storage media of a rewritable optical disk.
In the phase change memory, information storage is performed by using a difference between phase states of the chalcogenide. A phase change from the crystal state to the amorphous state or a reverse phase change from the amorphous state to the crystal state can be obtained by locally raising temperature of the chalcogenide. Although depending on the phase change material, its composition, and the like, both phases are generally stabilized at approximately 130° C. or lower so that information is stably retained. Also, when the chalcogenide is held at a crystallization temperature of 200° C. or higher for a sufficient period, the phase thereof changes to the crystal state. A crystallization time changes depending on the composition of the chalcogenide and the holding temperature. In a case of Ge2Sb2Te5, the crystallization time thereof is, for example, 150 nanoseconds. For returning the chalcogenide to the amorphous state, the temperature is raised to a melting point thereof (approximately 600° C.) or higher and rapidly lowered to cool.
As a method of raising the temperature, a current is carried to the chalcogenide to heat by Joule heat generated from an inside of the chalcogenide or an electrode adjacent thereto. Hereinafter, the crystallization of the chalcogenide of the phase change memory cell is called a “set operation”, and the amorphization thereof is called a “reset operation”. Also, a state in which a phase change portion has been crystallized is called a “set state”, and a state in which the phase change portion has been amorphized is called a “reset state”. A set time is, for example, 150 nanoseconds, and a reset time is, for example, 50 nanoseconds.
A reading method is as follows. A voltage is applied to the chalcogenide to measure a current passing through the chalcogenide, whereby a resistance value of the chalcogenide is read, and information is identified. When the chalcogenide is in the set state at this time, even if the temperature is raised up to the crystallization temperature, the set state is maintained because the chalcogenide is already crystallized. However, when the chalcogenide is in the reset state, the information is destroyed. Therefore, for causing no the crystallization, a reading voltage must be set to a feeble voltage of, for example, approximately 0.3 V. The phase change memory is characterized in that: the resistance value in the phase change portion also changes from two digits to three digits according to the crystal state or amorphous state; and since a magnitude of the resistance value is read so as to correspond to binary information of “0” and “1”, as the difference between the resistance values is larger, the sense operation is performed easier, and the read is performed at high speed. Hereinafter, the reading operation is called “read operation”.
As shown in FIG. 2, while a conventionally-known phase change memory cell 200 is mostly configured with a storage device 207 and a selecting transistor 208, a configuration of a cross-point type memory cell including no selecting transistor is also considered. The storage device 207 generally includes a chalcogenide 201, an upper electrode 203, and a plug electrode 202, the electrodes sandwiching the chalcogenide 201 therebetween. Normally, although the plug electrode 202 mostly takes a plug structure having a smaller contact area with the chalcogenide than that of the upper electrode 203, a thin film may be used as the electrode as described in Non-Patent Document 1. Note that “204” indicates a word line (WL), “205” indicates a source line, and “206” indicates a bit line (BL).
A general operation of the phase change memory is described in Non-Patent Document 2. The reset operation is performed by starting up the word line and applying a current pulse having a pulse width of 20 to 50 nanoseconds to the bit line. The set operation is performed by starting up the word line and applying a current pulse having a pulse width of 60 to 200 nanoseconds to the bit line. The read operation is performed by starting up the word line and applying a current pulse having a pulse width of 20 to 100 nanoseconds to the bit line. The current pulses used for the reset operation, the set operation, and the read operation flow from the bit line toward the source line in all of the operations or from the source line toward the bit line in all of the operations.
Compared to the set operation required for raising the temperature only up to the crystallization temperature, a larger current is required for the reset operation required for heating up to the melting point which is higher than the crystallization temperature. By reducing the current for the reset operation, an area size of a selected device is reduced so that high memory integration is made possible.    Patent Document 1: Japanese Patent Application Laid-Open Publication No. 2004-272975    Non-Patent Document 1: Y. H Ha and other 6 people, “An Edge Contact Type Cell for Phase Change RAM Featuring Very Low Power Consumption”, 2003 Symposium on VLSI Technology Digest Technical Papers, USA, 2003, p. 175-176    Non-Patent Document 2: H. Horii and other 7 people, “A Novel Cell Technology Using N-doped GeSbTe Films for Phase Change RAM”, 2003 Symposium on VLSI Technology Digest Technical Papers, USA, 2003, p. 177-178